Low Density Parity Check (“LDPC”) codes, originally invented in 1962 by Gallagher, have recently been utilized in various communications applications. Because LDPC codes are based on an iterative decoding scheme, the performance of an LPDC decoder is highly dependent upon the number of iterations available to properly decode the information. Under poor signal conditions, a decode instance can consume hundreds of iterations and still be on the road to convergence. As a matter of implementation, designing decoder architectures capable of achieving large iteration counts can be quite difficult. Systems with large block sizes and/or high data rates can further exacerbate the problem, placing a physical limit on the number of iterations that can be performed between code blocks. However, some systems may not require that a consistently large number of iterations be available for each code block. Nominally, these systems could be expected to converge in a much shorter number of cycles, and may only require additional iterations at sporadic instances. Decoder design could be made simpler for such systems provided that such design could also adequately support sporadic demands (which at some times are sustained over multiple code blocks) for high iteration counts.
What is thus needed in the art are systems and methods that can support a large number of iterations for decoding when necessary, but that also avoid a complex decoder design.